COSC3406 Decimal Integer Values

You need to type in your solution except for diagrams.

1. Using n= 8 bits and all of following internal representations for signed integers (30 marks):
2. Signed magnitude
3. one's complement
4. two's complement

Give the codes for each of the following signed decimal integer values, fill in values directly into the table below. Given each answer as a 2-digit hexadecimal value. It is not necessary to show your work (base conversion, twos complementing operations.

1. 1,234,567,090

2 1234567090

2 617283545 -0

2 308641772 -1

2 154320886 -0

2 77160443 -0

2 38580221 -1

2 19290110 -1

2 9645055 -0

2 4822527 -1

2 2411263 -1

2 1205631 -1

2 602815 -1

2 301407 -1

2 150703 -1

2 75351 -1

2 37675 -1

2 18837 -1

2 9418 -1

2 4709 - 0

2 2354 -1

2 1177 -0

2 588 -1

2 294 -0

2 147 -0

2 73 -1

2 36 -1

2 18 -0

2 9 -0

2 4 -1

2 2 0

2 1 0

0100 1001 1001 0101 1111 1111 1011 0010

= (4995FFD2)₁₆

2. -2,777,888,099

2 2777 888099

2 1388944059 -1

2 694472024 -1

2 347236012 -0

2 173618006 -0

2 86809003 -0

2 43404501 - 1

2 21702250 -1

2 10851125 -0

2 5425562 -1

2 2712781 -0

2 1356390 -1

2 678195 -0

2 339097 -1

2 169548 -1

2 84774 -0

2 42387 -0

2 21193 -1

2 10596 -1

2 5298 -0

2 2649 -0

2 1324 -1

2 662 -0

2 331 -0

2 165 -1

2 82 -1

2 41 -0

2 20 -1

2 10 -0

2 5 -0

2 2 -1

• 0

= (1101 0010 1100 1001 1001 1010 1011 0001)₁₆

= (D2C99AB1)₁₆

3. What signed decimal integer is represented by each of the following 32-bit two's complement representation? Show your work (15 marks).
4. 7E45E012

(7E45E012)₁₆ = (0111 1111 0100 0101 1110 0000 0001 0010)₂

1*2³⁰ +1*2²⁹ +1*2²⁸ + 1*2²⁷ +1*2²⁶+1*2²⁵ +1*2²⁴ + 0*2²³ +1*2²²+0*2²¹ +0*2²⁰

+ 0*2¹⁹ +1*2¹⁸+0*2¹⁷ +1*2¹⁶ + 1*2¹⁵+1*2¹⁴+1*2¹³ +0*2¹² + 0*2¹¹ +0*2¹⁰+0*2⁹ +0*2⁸

+ 0*2⁷ +0*2⁶+0*2⁵ +1*2⁴ + 0*2³ +0*2²+1*2¹ +0*2⁰

= 2,135,285,778

2. (EA66110B)₁₆

= (1111 1010 0110 0110 0001 0001 0000 1011)₂

The first letter has a negative (-ve)

1*2³⁰ +1*2²⁹ +1*2²⁸ + 1*2²⁷ +0*2²⁶+1*2²⁵ +0*2²⁴ + 0*2²³ +0*2²²+1*2²¹ +0*2²⁰

+ 0*2¹⁹ +1*2¹⁸+1*2¹⁷ +0*2¹⁶ + 0*2¹⁵+0*2¹⁴+0*2¹³ +1*2¹² + 0*2¹¹ +0*2¹⁰+0*2⁹ +1*2⁸

+ 0*2⁷ +0*2⁶+0*2⁵ +0*2⁴ + 1*2³ +0*2²+1*2¹ +1*2⁰

= -2,053,509,387

4. Using figures to illustrate the following addressing modes (30 marks):

• Immediate addressing
• Direct addressing
• Indirect addressing
• Register addressing
• Register indirect addressing
• Displacement addressing
• Relative addressing
• Base-register addressing
• index addressing

Solution

Immediate addressing mode involves data following instructions. As an illustration, the data that has to be used is already in the instruction itself. For instance, MOV A, #25H (This instruction moves data 25H to the accumulator. However, the # sign shows that the preceding term is data not address)

Direct addressing mode. Within this mode, the address of data to be read is directly given in the instruction. For instance, MOV A, 46H (This instruction will move the contents of memory location 46H to accumulator).

Instruction

Indirect addressingmode: The data is stored in registers or memory location indirectly. Conversely, the instruction set the memory location of the address of the data to be stored. E.g., MOV R2, 37H. The instruction moves the content of address present at 37H to register R2. 

register addressing mode: The source of data or destination of the result is registered. However, the name of the register is given in the instruction where the data to be read or result to be stored (Patterson & Hennessy, 2013). For example Add, R3, R4. The instruction adds the contents of register R4 to R3 and then store it to R3.

Register indirect addressing mode: The data is read or stored in register indirectly. The register is provided in the instruction where the address of the other register is stored or which points to other registers where data is stored or to be stored (Patterson & Hennessy, 2013). For instance, MOV A, @R0. This instruction will move the data to accumulator from the register whose address is stored in register R0.This is similar to the index mode except that instead of an index register, a base register will be used. The base register contains a pointer to a memory location.

mode is also called PC-relative addressing. The implicitly referenced register is the program counter (PC). The next instruction is added to the address field to produce the EA. The address field is usually treated as a twos complement number for this operation. Therefore, the effective address is a displacement relative to the address of the instructions (Patterson & Hennessy, 2013). For instance, Move X (PC), R1. The contents at address X+PC are moved to R1.X contains a constant value.

A version of displacement addressing

R = program counter, pc

EA = A + (PC)

Base-register addressing mode: This mode is similar to index addressing mode, but instead of suing index register it utilizes the value of base register which is called offset. For instance, MOV R2, BR + offset. This moves the content of effective address by adding BR and Offset to the register R2

A holds displacement

R holds pointer to base address

R may be explicit or implicit

Index addressing is the address of the operand which is obtained by adding to the contents of the general register a constant value. However, the number of the index register along with the constant value is included in the instruction code.

A = base

R = displacement

EA = A + R

This is therefore good for accessing arrays

5 An instruction is stored at location 200 with its address field at location 201. The address field has the value 300. A processor register R1 contains the number 100. Evaluate the effective address if the addressing mode of the instruction is a) direct; b) immediate; c) relative; d) register indirect; e) index with R1 as the index register

The instruction is stored at location 200 with address field at 201. However, the address field has the value 300. The processor register R1 has the number 100.

(a). Direct.

 To evaluate our addressing mode as direct, we pull the number from the value of the address field. In this case, the direct is 300.

(b). Immediate addressing mode

For the case of immediate addressing mode, we seek out the instruction stored location. In our case is 200 which is the answer.

(c) Relative

Concerning relative location, the formula for calculation is as follows:

Addressing Field Location + Processor Register = Relative Location

In this case, it is 201+ 100 = 301.

(d). Register indirect

The effective address for indirect register mode is 100.

(e).Index with R1 as the index register

The formula for getting this is;

Address Field Value + Processor Register = Indexed Location

300 + 100 = 400

6. A nonpipleline system takes 40ns to process a task. The same task can be processed in a six-segment pipeline with a clock cycle of 10 ns. Determine the speedup ratio of the pipeline for 80 tasks. What is the maximum speedup that can be achieved

Solution

The speedup ratio is defined as the speedup of a pipeline processing concerning the equivalent non-pipeline processing. The below is the formula for getting speed up ratio

S = t_en/ (K+n-1) tp

The number of tasks n = 80

For nonpipeline:

Time is taken by pipeline to process a task _in = 40 ns

Total time is taken by pipeline to process 80 task = t_en

= 80*40

= 3200 ns

For pipeline:

Number of segment pipeline K = 6

Time period of 1 clock t_p = 10 ns

Total time requires to complete n tasks in K segment pipeline with t_p clock cycle time:

= (k+n-1) t_p

= (6+ 80-1)10

= 850 ns

Speed up Ratio:

When the total time taken by the pipeline to process 80 is divided by the total time required to complete n tasks in K segment pipeline with tp clock cycle time then speed up ratio is obtained.

S = 3200/850

= 3.76

The speedup ratio of the pipeline for 80 tasks is therefore 3.76

Maximum speed up ration:

As the number of tasks increases, n becomes very small k+n-1 approaches to n, and hence the speed up ration becomes S_max = _nTN/t_p

Hence it is;

S_max = 40/10

= 4

In this case, the maximum speedup ratio that can be achieved is 4

References

Patterson, D. A., & Hennessy, J. L. (2013). Computer Organization and Design MIPS Edition: The Hardware/Software Interface. Newnes.

Organization/Textbooks/ComputerOrganizationAndDesign5thEdition2014.pdf.