IFN503 Fundamental Computer System
Question 1
What is the ASCII representation of each character in the string +35.95 in the following number systems?
- hexadecimal
- binary
- octal
Question 2
- Represent the fixed point decimal number-85.625 in IEEE 754 floating point format. Express your final answer in hexadecimal showing all the working.
- Consider a hypothetical floating point format which is similar to IEEE format except that it uses 6 bit excess-31 notation for the exponent and 25 bits for the mantissa in a 32 bit machine. Represent the decimal number from part (a) in hexadecimal using this hypothetical format. Show all the working.
Question 3
You have to output the result when the following expression is executed for two numbers: and .
- Draw a flowchart to do the above.
- Write aLittle Man Computer program that will produce the required output.
Answer:
1(a) Content at Instruction Register (IR): 550
Content at Program Counter (PC): 21
Content at MAR: 50
Content at MDR: 724
(b) At first step of fetch execution cycle the content will be as follows:
Instruction Register: 550, Program Counter: 21, Memory Address Register: 21, Memory Data Register: 151, Accumulator: 724
At 2nd stage
Instruction Register: 151, Program Counter: 22, Memory Address Register: 21, Memory Data Register: 151, Accumulator: 724
At 3rd stage
Instruction Register: 151, Program Counter: 22, Memory Address Register: 51, Memory Data Register: 006, Accumulator: 724
At 4th stage
Instruction Register: 151, Program Counter: 22, Memory Address Register: 51, Memory Data Register: 006, Accumulator: 730
- The MAR (Memory Address Register) contains the address of the block consisting instructions write or read and MDR (Memory Data Register) is associated with the data to be read or written in from the location suggested by MAR. The memory in MDR is made up of a group of cells; each cell has its own unique address and every cell can store only 1 bit. Whereas in MAR if addressing bits are made up of 4 bits then total address lines will be 24 = 16. MAR or Program Counter is used by LMC to fetch the address of the memory and it utilizes 100 of its memory cells as Memory Data Register. The real computer can be customized as per the user need by grouping cells of MAR to construct MAR. For example: If some MAR has a width of 3 bits and MDR is made up of 2 groups of memory cell. Total memory capacity would be 2 times of location of MAR that is 2 ×24bits.
- The ADD instruction for the modified LMC that need 2 consecutive locations for every instruction:
PC à MAR
MDR à IR [high]
PC + 1 à PC
PC à MAR
MDR à IR (low)
IR (low) à MAR
MDR à A
PC + 1 à PC
- In the mutant variation of LMC, LPC consists of one additional instruction known as MOVE which requires 2 consecutive words 0XX and 0YY. The fetch execution cycle for LPC MOVE instruction will be:
PC à MAR
MDRàIR
0XXà0YY
PC + 1 àPC
References
Bosky Agarwal (2004). "Instruction Fetch Execute Cycle" (PDF). Archived from the original (PDF) on June 11, 2009. Retrieved 07-09-18.
