EE 4363 CSCI 4203 Computer Architecture and Machine Organization Homework 2

EE 4363/CSCI 4203

COMPUTER ARCHITECTURE & MACHINE ORGANIZATION

FALL 2019 HOMEWORK II

10/03 - 10/15

1 [INSTRUCTION SET ARCHITECTURE]

The architects of the MN-4363 processor, Tim FlimFlam and Doug TickTock are exploring the ISA design space. (a) Tim claims that there is no need for a multiply instruction. A left shift should serve the purpose. Would this idea work? Justify your answer.

Note: Consider both positive and negative numbers.

[5pts]

1. Doug claims that it is not left shift, but left shift along with add that would suffice to implement multiply.

• Following Doug’s suggestion, demonstrate how multiply can be implemented by using left shift and add

Note: Consider only positive numbers.

[15pts]

• In multiplying two integers, X and Y, can the number of left shifts and adds required change as a function of the order in which the operands are processed: X × Y Y × X?

[5pts]

• Demonstrate how two 16-bit numbers, (121⁾₁₀ and (33⁾₁₀ can be multiplied using only add and shift: Doug’s technique from (b.ii).

[10pts]

2 [MIPS ASSEMBLY]

Your classmate, Tim FlimFlam is studying MIPS addressing formats.

• Tim thinks that PC-relative addressing for conditional branches is useless; if we interpreted the address (immediate) field to translate directly to the branch target address, we could have simplified the hardware significantly, he claims. How is Tim’s approach different from PC-relative addressing? Under which conditions would Tim’s suggestion work? [10pts]
• Tim identifies the maximum possible jump range as 1MB, examining pseudo-direct addressing. Do you agree with Tim’s observation? Explain. [5pts]
• Tim thinks that there is no need for jr instruction, since they can be synthesized using basic MIPS instructions. Demonstrate how possibly these instructions can be implemented by combining basic MIPS instructions, following Tim’s suggestion. [5pts]

3 [INSTRUCTION SET ARCHITECTURE]

The architect of the MN-4363 processor, Tim FlimFlam wants to design a (control flow) instruction which can change all bits of the PC. MN-4363 ISA is 32-bit, similar to MIPS. MN-4363 ISA assumes the same addressing modes as MIPS. [20pts]

• Demonstrate how all bits of the PC can be changed by using a single instruction, using register-addressing.

Can a single instruction to change all bits of the PC be designated using immediate-addressing?

[3pts]

• Demonstrate how all bits of the PC can be changed by using a chain of MIPS-like pseudo-direct jumps only. What is the maximum jump range? How would the maximum jump range change as a function of the chain length?

[5pts]

• Demonstrate how all bits of the PC can be changed by using a chain of MIPS-like pseudo-direct jumps and conditional branches.

[7pts]

• Compare and contrast the implications of the three implementations from (a)-(c) for jump range and compiler complexity.

[5pts]

4 [MIPS ASSEMBLY]

Provide an assembly language version of the following C code segment. At the beginning of this code segment, the only values in registers are the base address of arrays A and B in registers $a0 and $a1.

[25pts]

5 NOTES

• Please submit an electronic copy in pdf format.
• Any dangling answer without justification deserves 0 points at most.